Imaging devices such as complementary metal oxide semiconductor (CMOS) imagers are commonly used in photo-imaging applications.
A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate, photoconductor or photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
A typical CMOS imager 10 is illustrated in FIG. 1. The imager 10 includes a pixel array 20 connected to column sample and hold (S/H) circuitry 30. The pixel array 20 comprises a plurality of pixels arranged in a predetermined number of rows and columns (e.g., M rows and N columns). In operation, the pixels of each row in the array 20 are all turned on at the same time by a row select line and the pixels of each column are selectively output by a column select line. A plurality of row and column lines are provided for the entire array 20.
The row lines are selectively activated by row control circuitry 16 in response to an applied row address. The column select lines are selectively activated by column control circuitry 18 in response to an applied column address. Thus, a row and column address is provided for each pixel. The CMOS imager 10 is operated by the row and column control circuits 16, 18, which controls the row and column circuitry for selecting the appropriate row and column lines for pixel readout. Column control circuit 18 includes a column decoder 907.
The CMOS imager 10 illustrated in FIG. 1 uses a dual channel readout architecture. That is, the imager 10 includes a first channel ChA and a second channel ChB for pixel image and reset signals (the “pixel signals”) read out of the array 20. Each readout channel ChA, ChB is used to read out half the number of pixels connected to the column S/H circuitry 30. As is known in the art, once read out, the analog reset and pixel signals pass through a readout chain 80, 82 controlled by readout control circuitry 84. Each readout chain 80, 82 may include an amplifier 901 (FIG. 1), gain stage circuit 902 which includes a gain stage amplifier 904 (FIG. 1) and an analog-to-digital converter (ADC) 903 (FIG. 1), before being processed as digital signals by an image processor. Since each channel ChA, ChB contains its own readout chain 80, 82, there exists an offset and slight gain difference due to process mismatches.
Many imagers use the Bayer color filter array (CFA) scheme for its pixel arrays. Other imagers may use complementary filters having cyan, magenta, and yellow filters. FIG. 2 illustrates the Bayer scheme for the pixel array 20 illustrated in FIG. 1. Each row of pixels contains two types of CFA's. Row0, for example, contains alternating green 22 (designated as Gr) and red 24 (designated as R) pixels, while Row1 contains alternating blue 26 (designated as B) and green 28 (designated as Gb) pixels. To ensure that the green pixels 22, 28 (Gr, Gb) have the same offset and gain, the signals from the green pixels need to be transferred from the column S/H circuitry 30 to the same channel, e.g., ChA. Further in other aspects, digital correction may be applied to the signals to correct for any remaining offset which would require logic and circuitry not depicted in FIG. 2. Therefore, the first channel ChA will readout the signals from the green pixels 22, 28 (Gr, Gb) while the second channel ChB will readout the signals from the red and blue pixels 24, 26 (R, B).
FIG. 3 is a circuit diagram of the imager 10 illustrated in FIG. 1. The pixel array 20 comprises M rows and N columns. As can be seen in FIG. 3, the column S/H circuitry 30 comprises multiple column S/H sub-circuits 30_0, 30_1, . . . 30_n−1, one for each column in the array 20. Each sub-circuit 30_0, 30_1, . . . 30_n−1 is respectively connected to a pixel output line pixout_0, pixout_1, . . . , pixout_n−1. The first output channel ChA includes two output lines 70, 72. The second output channel ChB contains two output lines 74, 76. During operation of the imager 10, the pixel output lines pixout_0, pixout_1, . . . , pixout_n−1 carry reset and pixel signals from their respective associated pixels in the array 20.
The column control circuitry 18 provides a column 0 select signal colsel_0, column 0 green pixel select signal colsel0_A, and a column 0 red/blue select signal colsel0_B to the column 0 (first) S/H sub-circuit 30_0. Similarly, the column control circuitry 18 provides a column 1 select signal colsel_1, column 1 green pixel select signal colsel1_A, and a column 1 red/blue select signal colsel1_B to the column 1 (second) S/H sub-circuit 30_1. A global crowbar control signal CB, sample and hold pixel control signal SHS and a sample and hold reset control signal SHR are also provided to the column S/H sub-circuits 30_0, 30_1, . . . 30_n−1. The use of these signals CB, SHS, SHR are described below in more detail.
The global crowbar control signal CB is input into an AND gate 38_0 of the column 0 S/H sub-circuit 30_0. The second input of the AND gate 38_0 is connected to the column 0 select signal colsel_0. The output of the AND gate 38_0 is a crowbar control/select column 0 signal CBsel_0, which is generated only when the colsel_0 and CB signals are activated at the same time.
The column 0 S/H sub-circuit 30_0 also comprises a biasing transistor 32_0, controlled by a control voltage Vln, that is used to bias its respective pixel output line pixout_0. The pixel output line pixout_0 is also connected to a first capacitor 42_0 thru a sample and hold pixel signal switch 34_0. The sample and hold pixel signal switch 34_0 is controlled by the sample and hold pixel control signal SHS. In addition, the pixel output line pixout_0 is connected to a second capacitor 44_0 thru a sample and hold reset signal switch 36_0. The sample and hold reset signal switch 36_0 is controlled by the sample and hold reset control signal SHR. The switches 34_0, 36_0 are typically MOSFET transistors, but may also be CMOS switches.
A second terminal of the first capacitor 42_0 is connected to the first ChB pixel output line 74 via a first column select switch 50_0, which is controlled by the colsel0_B signal. The second terminal of the first capacitor 42_0 is also connected to the first ChA pixel output line 70 via a second column select switch 52_0, which is controlled by the colsel0_A signal. The second terminal of the first capacitor 42_0 is also connected to a clamping voltage VCL via a first clamping switch 60_0.
The second terminal of the second capacitor 44_0 is further connected to the second ChA pixel output line 72 via a third column select switch 54_0, which is controlled by the colsel0_A signal. The second terminal of the second capacitor 44_0 is also connected to the second ChB pixel output line 76 via a fourth column select switch 56_0, which is controlled by the colsel0_B signal. The second terminal of the second capacitor 44_0 is also connected to the clamping voltage VCL via a second clamping switch 62_0.
The four column select switches 50_0, 52_0, 54_0, 56_0 are part of a multiplexer 58, the operation of which is described below in more detail. The multiplexer 58 also comprises additional column select switches (e.g., 50_1, 52_1, 54_1, 56_1) from the remaining column S/H sub-circuits 30_1, . . . , 30_n−1. The column select switches 50_0, 52_0, 54_0, 56_0, 50_1, 52_1, 54_1, 56_1 are typically MOSFET transistors.
As is known in the art, the clamping voltage VCL is used to place a charge on the two capacitors 42_0, 44_0 when it is desired to store the pixel and reset signals, respectively from the array 20 (when the appropriate S/H control signals SHS, SHR are also generated).
Connected between the connection of the first capacitor 42_0 and its sample and hold switch 34_0 and the connection of the second capacitor 44_0 and its sample and hold switch 36_0 is a crowbar switch 40_0. The crowbar switch 40_0 is controlled by the CBsel_0 output from the AND gate 38_0. During readout of column 0, the column 0 S/H sub-circuit 30_0 is selected by the colsel_0 signal, the global crowbar control signal CB is also generated, which causes the CBsel_0 signal to be output from the AND gate 38_0. As such, crowbar switch 40_0 is closed, which shorts the front plates of the two capacitors 42_0, 44_0, driving the respective charges on these capacitors 42_0, 44_0 out to the multiplexer 58.
Similar to the column 0 S/H sub-circuit 30_0, the global crowbar control signal CB is input into an AND gate 38_1 of the column 1 S/H sub-circuit 30_1. The second input of the AND gate 38_1 is connected to the column 1 select signal colsel_1. The output of the AND gate 38_1 is a crowbar control/select column 1 signal CBsel_1, which is generated only when the colsel_1 and CB signals are activated at the same time. The remainder of the column 1 S/H sub-circuit 30_1 is essentially the same as the column 0 S/H sub-circuit 30_0. Thus, no further description of the column 1 S/H sub-circuit 30_1 is required.
Assuming that even numbered rows (e.g., Row0, Row2, etc.) have green pixels 22 (Gr) in even numbered columns (e.g., Col0, Col2, etc.) and red pixels 24 in odd numbered columns (e.g., Col1, Col3, etc.), then according to the Bayer CFA pattern, odd rows (e.g., Row1, Row3, etc.) have green pixels 28 (Gb) in the odd numbered columns and blue pixels 26 in the even numbered columns.
Referring to FIGS. 2 and 3, in operation, the signals from the pixels from Row0 are sampled onto the S/H circuitry 30 first. Even numbered column S/H circuitry (e.g., sub-circuit 30_0) will receive the signals from the green pixels 22 (Gr) from Row0. Odd numbered column S/H circuitry (e.g., sub-circuit 30_1) will receive the signals from the red pixels 24 (R) from Row0. To make sure the signals from the Row0 green pixels 22 go to the first channel ChA, and the signals from the red pixels 24 go to the second channel ChB, the multiplexer 58 described above is included within the column S/H circuitry just prior to the readout lines 70, 72, 74, 76 to the channels ChA, ChB.
Thus, during the readout operation performed on Row0, the column select switch/transistors 52_0, 54_0 connected to the first channel ChA in each even numbered column (e.g., Col0, Col2, etc.) must be selected in the multiplexer 58. In addition, during the readout operation performed on Row0, the column select switch/transistors 50_1, 56_1 connected to the second channel ChB in each odd numbered column (e.g., Col1, Col3, etc.) must be selected in the multiplexer 58.
When the Row1 signals are sampled onto the column S/H circuitry 30_0, 30_1, . . . , 30_n−1, the even numbered columns (e.g., Col0, Col2, etc.) will have the signals from the blue pixels 26 and the odd numbered columns (e.g., Col1, Col3, etc.) will have the signals received from the green pixels 28 (Gb). Thus, during the readout operation performed on Row1, the column select switch/transistors 52_1, 54_1 connected to the first channel ChA in each odd numbered column (e.g., Col1, Col3, etc.) must be selected in the multiplexer 58. In addition, during the readout operation performed on Row1, the column select switch/transistors 50_0, 56_0 connected to the second channel ChB in each even numbered column (e.g., Col0, Col2, etc.) must be selected in the multiplexer 58.
Signals readout onto the first channel ChA are provided to the first readout chain A (e.g., readout chain 80 of FIG. 1) for processing, which, as indicated above may include an amplifier, gain stage and an analog-to-digital converter (ADC), before being processed as digital signals by an image processor (not shown). Similarly, signals readout onto the second channel ChB are provided to the second readout chain B (e.g., readout chain 82 of FIG. 1) for processing, which, as indicated above may include an amplifier, gain stage and an analog-to-digital converter (ADC), before being processed as digital signals by an image processor (not shown). The processing of signals by the first readout chain A is independent of, and can be done in parallel with, the processing of signals by the second readout chain B.
This use of multiple readout chains decreases the time in which to process all of the signals received from a pixel array. However, this architecture has some drawbacks as each signal readout chain A, B consumes power to process the signals.
As the demand for higher resolution sensors increases, the power consumption of the imager device also increases. In certain applications, power consumption is an important design consideration. For example, in mobile applications where the supply of power may be limited, power consumption must be limited.
One approach to limiting power consumption is to provide variable sensing modes. For example, a first sensing mode includes a high resolution mode, where all of the pixels of the imager device are readout and processed. The first sensing mode is used to capture the highest resolution image. A second sensing mode includes a lower resolution mode, where only some of the pixels of the imager device are readout and processed. The second sensing mode is used for “viewfinder” (e.g., monitor) applications, where a lower resolution may be used.
However, even though power consumption is decreased by the use of a lower resolution mode, imager devices having multiple readout chains still consume a great deal of power.
Accordingly, there is a need and desire for a multiple readout chain scheme for an imager having reduced power consumption than prior art multiple readout schemes.